AJ van de Goor, GN Gaydadjiev, S Hamdioui (2010), Memory testing with a RISC microcontroller, s.n. (Eds.), In Design, automation & test in Europe 2010 p.214-219.

NZB Haron, S Hamdioui (2010), Mitigating defective CMOS to non-CMOS vias in CMOS/molecular memories, s.n. (Eds.), In IEEE nano 2010 p.1-4.

MSK Seyab, S Hamdioui (2010), NBTI modeling in the framework of temperature variation, s.n. (Eds.), In Design, automation & test in Europe p.1-4.

M Taouil, S Hamdioui, J Verbree, E Marinissen (2010), On maximizing the compound yield for 3D wafer-to-wafer stacked ICs, s.n. (Eds.), In Intl. TEST conference 2010 p.1-10.

NZB Haron, S Hamdioui (2010), Redundant residue number system code for fault-tolerant hybrid memories, In ACM Journal on Emerging Technologies in Computing Systems p.1-19.

MSK Seyab, S Hamdioui (2010), Temperature dependence of NBTI induced delay, s.n. (Eds.), In 16th IEEE intl. on-line testing symposium p.1-6.

MSK Seyab, S Hamdioui (2010), Temperature impact on NBTI modeling in the framework of technology scaling, Y Patt, P Foglia, E Duesterwald, P Faraboschi, X Martorell (Eds.), In 5th Intl. conf, HIPEAC 2010 p.1-10, Springer.

M Taouil, S Hamdioui, CIM Beenakker, E Marinissen (2010), Test cost analysis for 3D die-to-wafer stacking, s.n. (Eds.), In Proc. of the 19th Asian test symposium p.435-441.

MSK Seyab, S Hamdioui (2010), Trends and challenges of SRAM reliability in the nano-scale era, s.n. (Eds.), In 2010 intl. conf. on design & technology of integrated systems in nanoscale Era p.1-6.

AJ van de Goor, S Hamdioui, GN Gaydadjiev (2010), Using a CISC microcontroller to test embedded memories, s.n. (Eds.), In IEEE intl. symposium on design and diagnostics of electronic circuits and systems p.382-387.