MSK Seyab, S Hamdioui (2011), Modeling and Mitigating NBTI in Nanoscale Circuits, M Nicolaidis, A Paschalis, D Gizopoulos, X Vera (Eds.), In Proceedings of IEEE International On-Line Testing Symposium (IOLTS 2011) p.3-8.

MSK Seyab, S Hamdioui (2011), NBTI-Aware Nanoscaled Circuit Delay Assessment and Mitigation, A Orailoglu, MK Michael, Y Sazeides, T Theocharides (Eds.), In Proceedings of 3rd Workshop on Design for Reliability (DFR'11) p.1-10.

MSK Seyab, NZB Haron, S Hamdioui, F Catthoor (2011), NBTI Monitoring and Design for Reliability in Nanoscale Circuits, G Chapman, F Salice, PD Joshi, M Violante (Eds.), In IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2011) p.68-76.

NZB Haron, S Hamdioui (2011), On Correcting Cluster Errors in Nanoelectronic Memories, A Orailoglu, MK Michael, Y Sazeides, T Theocharides (Eds.), In Proceedings of 3rd Workshop on Design for Reliability (DFR'11) p.63-68.

NZB Haron, S Hamdioui (2011), On Defect Oriented Testing for Hybrid CMOS/memristor Memory, A Chatterjee, A Patra, S Kundu, S Ravi (Eds.), In 20th IEEE Asian Test Symposium 2011 p.353-358.

M Taouil, S Hamdioui, E Marinissen (2011), On Modeling and Optimizing Cost in 3D Stacked-ICs, M Sawan, H Harmanani (Eds.), In 6th IEEE International Design and Test Workshop during ICECS 2011 p.24-29.

AJ van de Goor, H Kukner, S Hamdioui (2011), Optimizing Memory BIST Address Generator Implementations, S Bernard, C Efstathiou (Eds.), In Proceedings 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era p.1-6.

NZB Haron, S Hamdioui (2011), Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories, In ACM Journal on Emerging Technologies in Computing Systems Volume 7 p.1-19.

MSK Seyab, S Hamdioui (2011), ReverseAge: an Online NBTI Combating Technique Using Time Borrowing, M Sawan, H Harmanani (Eds.), In 6th IEEE International Design and Test Workshop (IDT 2011) p.36-41.

M Taouil, S Hamdioui (2011), Stacking Order Impact on Overall 3D Die-to-Wafer Stacked-IC Cost, R Kraemer, A Steininger, A Pawlak, et al. (Eds.), In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems p.335-340.