MSK Seyab, S Hamdioui, M Taouil, H Kukner, P Raghavan, F Catthoor (2012), Impact of partial resistive defects and bias temperature instability on SRAM decoder reliablity, s.n. (Eds.), In International design & test symposium p.1-6.

MSK Seyab, S Hamdioui, H Kukner, P Raghavan, F Catthoor (2012), Incorporating Parameter Variations in BTI Impact on Nano-scale Logical Gates Analysis, s.n. (Eds.), In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems p.1-6.

AM Monteiro OliveiraCortez, A Dargar, GJ Schrijen, S Hamdioui (2012), Modeling SRAM Start-Up Behavior for Physical Unclonable Functions, s.n. (Eds.), In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems p.1-6.

M Taouil, S Hamdioui (2012), On Optimizing Test Cost for Wafer-to-Wafer 3D Stacked ICs, s.n. (Eds.), In 7th International conference on design & technology of integrated systems in nanoscale era p.1-6.

M Taouil, S Hamdioui (2012), Yield improvement for 3D wafer-to-wafer stacked memories, In Journal of Electronic Testing: theory and applications Volume 28 p.523-534.

NZB Haron, S Hamdioui (2011), Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories, BM Al-Hashimi, W Rosenstiel (Eds.), In Proceedings Design, Automation and Test in Europe Conference and Exhibition (DATE 2011) p.265-268.

Z Al-Ars, GN Gaydadjiev, AJ van de Goor, S Hamdioui (2011), Generic march element based memory built-in self test.

M Taouil, S Hamdioui, E Marinissen (2011), How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs?, I Voyiatzis, H-J Wunderlich (Eds.), In 6th International conference on Design & Technology of Integrated Systems in nanoscale era p.1-6.

M Taouil, S Hamdioui (2011), Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories, EJ Aas, L. Anghel (Eds.), In 16th IEEE European Test Symposium p.45-50.

IS Irobi, Z Al-Ars, S Hamdioui (2011), Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs.