M Taouil, S Hamdioui, EJ Marinissen (2014), Quality versus cost analysis for 3D Stacked ICs, C Thibeault (Eds.), In Proceedings - 32nd IEEE VLSI Test Symposium p.1-6.

PD Joshi, A Sen, S Hamdioui, K Bertels (2014), Region disjoint paths in a class of optimal line graph networks, D El Baz, X Liu, CH Hsu, K Kang, W Chen (Eds.), In Proceedings - 17th IEEE International Conference on Computational Science and Engineering (CSE 2014) p.1256-1260.

PD Joshi, S Hamdioui (2014), Security methods in fault tolerant modified line graph based networks, M Ottavi, S Hamdioui (Eds.), In Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) p.57-62.

PD Joshi, S Hamdioui (2014), Shortest path reduction in a class of uniform fault tolerant networks, M Ottavi, S Hamdioui (Eds.), In Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) p.234-239.

AMMO Cortez, G Roelofs, S Hamdioui, G. di Natale (2014), Testing methods for PUF-based secure key storage circuits, In Journal of Electronic Testing: theory and applications Volume 30 p.581-594.

AMMO Cortez, G Roelofs, S Hamdioui, G. di Natale (2014), Testing PUF-based secure key storage circuits, G Fettweis, W Nebel (Eds.), In Proceedings of the 2014 International Conference on Design, Automation & Test in Europe p.1-6.

AM Monteiro OliveiraCortez, V van der Leest, R Maes, GJ Schrijen, S Hamdioui (2013), Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs, s.n. (Eds.), In IEEE International symposium on hardware-oriented security and trust p.35-40.

C Papameletis, B Keller, V Chickermane, EJ Marinissen, S Hamdioui (2013), Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers, s.n. (Eds.), In 18th IEEE European Test Symposium p.1-6.

MSK Seyab, S Hamdioui, H Kukner, P Raghavan, F Catthoor (2013), Bias temperature instability analysis in SRAM decoder, P Girard, Z Peng (Eds.), In Proceedings 18th IEEE European Test Symposium p.1-1.

M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik (2013), Impact of mid-bond testing in 3D stacked ICs, s.n. (Eds.), In 16th IEEE Symposium on defect and fault tolerance in VLSI and nanotechnology systems p.1-6.