NZB Haron, S Hamdioui (2009), Residue-based code for reliable hybrid memories, s.n. (Eds.), In 2009 IEEE/ACM international symposium on nanoscale architectures p.27-32, IEEE Society.

S Hamdioui, Z Al-Ars (2009), Scan more with memory scan test, s.n. (Eds.), In 4th IEEE international conference on design & technology of integrated systems in nanoscale era p.204-209, IEEE Society.

NZB Haron, S Hamdioui (2009), Using RRNS codes for cluster faults tolerance in hybrid memories, D Gizopoulos, M Tehranipoor, S Tragoudas (Eds.), In 2009 IEEE international symposium on defect and fault tolerance in VLSI systems p.85-93, IEEE Society.

S Hamdioui, Z Al-Ars, J Jimenez, J Calero (2008), BIST enhancement for detecting bit/byte write enable faults in SOC SCRAMs, s.n. (Eds.), In 2nd IEEE Intl. Conf. on Signals, Circuits & Systems p.1-5, IEEE Society.

MSK Seyab, NZB Haron, S Hamdioui (2008), CMOS scaling impacts on reliability, what do we understand?, s.n. (Eds.), In 19th Annual Workshop on Circuits, Systems and Signal Processing p.260-266, STW.

Z Al-Ars, S Hamdioui, AJ van de Goor, G Mueller (2008), Defect oriented testing of the strap problem under process variations in DRAMs, s.n. (Eds.), In Proc. International Test Conference 2008 p.1-10, ITC.

S Hamdioui (2008), Design and test of integrated circuits in Nano era: what is next?, 2008 International Conference on Signals, Circuits and Systems.

S Hamdioui, Z Al-Ars (2008), Efficient tests and DFT for RAM address decoder delay faults, s.n. (Eds.), In 3rd International Design and Test workshop p.225-230, IEEE Society.

NZB Haron, S Hamdioui (2008), Emerging crossbar-based hybrid nanoarchitectures for future computing systems, s.n. (Eds.), In 2nd IEEE Intl. Conf. on Signals, Circuits & Systems p.1-6, IEEE Society.

Z Al-Ars, S Hamdioui (2008), Evaluation of SRAM faulty behavior under bit line coupling, s.n. (Eds.), In 3rd International Design and Test workshop p.231-236, IEEE Society.