Peyman Pouyan, Esteve Amat, Said Hamdioui, Antonio Rubio (2016), RRAM Variability and its Mitigation Schemes, In 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 p.141-146.

Jintao Yu, Razvan Nane, Adib Haron, Said Hamdioui, H Corporaal, Koen Bertels (2016), Skeleton-based design and simulation flow for Computation-in-Memory architectures, W. Zhao, C.A. Moritz (Eds.), In 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) p.165-170, Association for Computing Machinery (ACM).

Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels (2016), Synthesizing HDL to Memristor Technology: A Generic Framework, W. Zhao, C.A. Moritz (Eds.), In 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) p.43-48, Association for Computing Machinery (ACM).

S Hamdioui, M Taouil, NZB Haron (2016), Testing open defects in memristor-based memories, In IEEE Transactions on Computers Volume 64 p.247-259.

C Papameletis, B Keller, V Chickermane, S Hamdioui, EJ Marinissen (2015), A DfT architecture and tool flow for 3-D SICs with test data compression, embedded cores, and multiple towers, In IEEE Design & Test Volume 32 p.40-48.

A Gebregiorgis, M Ebrahimi, S Kiamehr, F Oboril, S Hamdioui, MB Tahoori (2015), Aging mitigation in memory arrays using self-controlled bit-flipping technique, K Uchiyama (Eds.), In Proceedings - 20th Asia and South Pacific Design Automation Conference p.231-236.

IO Agbo, M Taouil, S Hamdioui, P Weckx, S Cosemans, F Catthoor (2015), BTI analysis of SRAM write driver, F Kurdahi, S Mir, MO Yu (Eds.), In Proceedings of the 10th International Design and Test Symposium, IDT 2015 p.100-105.

IO Agbo, M Taouil, S Hamdioui, S Cosemans, P Weckx, P Raghavan, F Catthoor (2015), Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier, V Casola (Eds.), In Proceedings - 10th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2015 p.1-6.

HA Du Nguyen, L Xie, M Taouil, R Nane, S Hamdioui, K Bertels (2015), Computation-in-memory based parallel adder, CA Moritz, M Rahman (Eds.), In Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH p.57-62.

M Ottavi, S Pontarelli, D Gizopoulos, A Paschalis, C Bolchini, MK Michael, L Anghel, M Tahoori, P Reviriego, O Bringmann, V Izosimov, H Manhaeve, C Strydis, S Hamdioui (2015), Dependable multicore architectures at nanoscale: The view from Europe, In IEEE Design & Test of Computers Volume 32 p.17-28.