NZB Haron, S Hamdioui (2011), Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories, BM Al-Hashimi, W Rosenstiel (Eds.), In Proceedings Design, Automation and Test in Europe Conference and Exhibition (DATE 2011) p.265-268, IEEE Society.

Z Al-Ars, GN Gaydadjiev, AJ van de Goor, S Hamdioui (2011), Generic march element based memory built-in self test.

M Taouil, S Hamdioui, E Marinissen (2011), How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs?, I Voyiatzis, H-J Wunderlich (Eds.), In 6th International conference on Design & Technology of Integrated Systems in nanoscale era p.1-6, IEEE Society.

M Taouil, S Hamdioui (2011), Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories, EJ Aas, L. Anghel (Eds.), In 16th IEEE European Test Symposium p.45-50, IEEE Society.

IS Irobi, Z Al-Ars, S Hamdioui (2011), Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs, 2011 16th IEEE European Test Symposium (ETS2011).

MSK Seyab, S Hamdioui (2011), Modeling and Mitigating NBTI in Nanoscale Circuits, M Nicolaidis, A Paschalis, D Gizopoulos, X Vera (Eds.), In Proceedings of IEEE International On-Line Testing Symposium (IOLTS 2011) p.3-8, IEEE Society.

MSK Seyab, NZB Haron, S Hamdioui, F Catthoor (2011), NBTI Monitoring and Design for Reliability in Nanoscale Circuits, G Chapman, F Salice, PD Joshi, M Violante (Eds.), In IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2011) p.68-76, IEEE Society.

MSK Seyab, S Hamdioui (2011), NBTI-Aware Nanoscaled Circuit Delay Assessment and Mitigation, A Orailoglu, MK Michael, Y Sazeides, T Theocharides (Eds.), In Proceedings of 3rd Workshop on Design for Reliability (DFR'11) p.1-10, HiPEAC.

NZB Haron, S Hamdioui (2011), On Correcting Cluster Errors in Nanoelectronic Memories, A Orailoglu, MK Michael, Y Sazeides, T Theocharides (Eds.), In Proceedings of 3rd Workshop on Design for Reliability (DFR'11) p.63-68, HiPEAC.

NZB Haron, S Hamdioui (2011), On Defect Oriented Testing for Hybrid CMOS/memristor Memory, A Chatterjee, A Patra, S Kundu, S Ravi (Eds.), In 20th IEEE Asian Test Symposium 2011 p.353-358, IEEE Society.