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S Vassiliadis, GN Gaydadjiev, KLM Bertels, E Panainte (2003), The molen programming paradigm, In Third international workshop on systems, architectures, modeling, and simulation p.1-7.

O Bonorden, BHH Juurlink, I von Otte, I Rieping (2003), The Paderborn University BSP (PUB) library, In Parallel Computing Volume 29 p.187-207.

MJ Geuzebroek, AJ van de Goor (2003), TPI for improving PR fault coverage of Boolean and three-state circuits, s.n. (Eds.), In ETW 2003; Eighth IEEE European test workshop p.3-8.

BHH Juurlink (2003), Unified dual data caches, s.n. (Eds.), In DSD 2003; euromicro symposium on digital system design, architectures, methodes and tools p.33-41.

CR Lageweg, SD Cotofana, S Vassiliadis (2002), 7/3 and 7/2 Counters implemented in single electron technology, In Proceedings of ProRISC 2002 p.344-350.

GK Kuzmanov, S Vassiliadis, JTJ van Eijndhoven (2002), A 2D adressing mode for multimedia applications, EF Deprettere, J Teich, S Vassiliadis (Eds.), In Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS p.291-307, Springer.

MD Padure, SD Cotofana, S Vassiliadis (2002), A CMOS flip-flop featuring embedded threshold logic functions, In Proceedings ProRISC 2002 p.388-392.

AJ van de Goor, I Schanstra (2002), Address and data scrambling: causes and impact on memory tests, M Renovell, et al. (Eds.), In International workshop on Electronic design, test, and applications p.128-137.

CR Lageweg, SD Cotofana, S Vassiliadis (2002), A family of single electron static buffered Boolean logic, In Proceedings of ProRISC 2002 p.339-343.