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S Vassiliadis, BHH Juurlink, EA Hakkennes (2000), Complex streamed instructions: introduction and initial evaluation, In Proceedings, vol. 1 p.400-408, IEEE.

S Vassiliadis, B Blaner (2000), Compounding preprocessor for cache.

SD Cotofana, BHH Juurlink, S Vassiliadis (2000), Counter based superscalar instruction issuing, In Proceedings, vol. 1 p.307-315, IEEE.

GG Pechanek, LD Larsen, CJ Glossner, S Vassiliadis (2000), Distributed processing array with component processors performing customized interpretation of instructions.

S Vassiliadis, M Zhang, JG Delgado-Frias (2000), Elementary function generators for neural-network emulators, In IEEE Transactions on Neural Networks Volume 11 p.1438-1449.

H Corporaal (2000), Embedded processor design using transport triggered architectures, R Creutzburg, K Egiazarian (Eds.), In SPECLOG'2000 proceedings p.469-469, TTKK.

A Berlea, SD Cotofana, I Athanasiu, CJ Glossner, S Vassiliadis (2000), Garbage collection for the Delft Java Processor, MH Hamza (Eds.), In Proceedings p.232-238, iASTED.

JSSM Wong, SD Cotofana, S Vassiliadis (2000), General-purpose Huffman encoding extension, In ITCC 2000 p.158-163, IEEE.

VM Stanca, S Vassiliadis, SD Cotofana, H Corporaal (2000), Hashed addressed caches for embedded pointer based codes, In In: A Bode, ...(et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900] p.956-968, Springer.