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S Vassiliadis, SD Cotofana, P Stathis (2000), Block based compression storage expected performance, NJ Dimopoulos, KF Li (Eds.), In HPC 2000: proceeding p.389-406, Kluwer Academic Publishers.

B Blaner, TL Jeremiah, S Vassiliadis, PG Williams (2000), Branch instruction processor and method.

PG D'Arcy, S Jinturkar, CJ Glossner, S Vassiliadis (2000), Compiler controlled dynamic scheduling of program instructions.

S Vassiliadis, BHH Juurlink, EA Hakkennes (2000), Complex streamed instructions: introduction and initial evaluation, In Proceedings, vol. 1 p.400-408, IEEE.

S Vassiliadis, B Blaner (2000), Compounding preprocessor for cache.

SD Cotofana, BHH Juurlink, S Vassiliadis (2000), Counter based superscalar instruction issuing, In Proceedings, vol. 1 p.307-315, IEEE.

GG Pechanek, LD Larsen, CJ Glossner, S Vassiliadis (2000), Distributed processing array with component processors performing customized interpretation of instructions.

S Vassiliadis, M Zhang, JG Delgado-Frias (2000), Elementary function generators for neural-network emulators, In IEEE Transactions on Neural Networks Volume 11 p.1438-1449.

H Corporaal (2000), Embedded processor design using transport triggered architectures, R Creutzburg, K Egiazarian (Eds.), In SPECLOG'2000 proceedings p.469-469, TTKK.