EB Tuncer, Z Al-Ars, E Akar, J Beintema, IS Sariyildiz (2006), Designmap: capturing design knowledge in architectural practice, M Dulaimi (Eds.), In Conference Proceedings of The Joint International Conference on Construction Culture, Innovation and Management (CCIM) p.352-361, BUiD.

Z Al-Ars, S Hamdioui, AJ van de Goor, S Al-Harbi (2006), Influence of bit line coupling and twisting on the faulty behavior of DRAMs, In IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems Volume 25 p.2989-2996.

S Hamdioui, Z Al-Ars, AJ van de Goor (2006), Opens and delay faults in CMOS RAM address decoder, In IEEE Transactions on Computers Volume 55 p.1630-1639.

Z Al-Ars, S Hamdioui, AJ van de Goor (2006), Space of DRAM fault models and corresponding testing, s.n. (Eds.), In Design Automation & Test in Europe DATE 06 p.1252-1257, IEEE Society.

S Hamdioui, Z Al-Ars, LL Mhamdi, GN Gaydadjiev, S Vassiliadis (2006), Trends in tests and failure mechanisms in deep sub-micron technologies, P Girard, M Masmoudi, J Mouine, M Renovell (Eds.), In 2006 International conference on Design & Test of Integrated Systems in Nanoscale Technology p.216-221, IEEE Society.

Z Al-Ars, S Hamdioui, GN Gaydadjiev (2006), Using linear tests for transient faults in DRAMs, s.n. (Eds.), In International Design and Test workshop p.-, IEEE Society.

Z Al-Ars (2005), DRAM fault analysis and test generation, PhD Thesis Delft University of Technology.

Z Al-Ars, S Hamdioui, G Mueller, AJ van de Goor (2005), Framework for fault analysis and test generation in drams, s.n. (Eds.), In Proceedings of design, automation and test in Europe 2005 (DATE 05) p.100-105, IEEE Society.

S Hamdioui, Z Al-Ars, AJ van de Goor, R Wadsworth (2005), Impact of stresses on the fault coverage of memory tests, s.n. (Eds.), In Proceedings of the IEEE international workshop on memory technology, design and testing p.103-108, IEEE Society.

Z Al-Ars, S Hamdioui, AJ van de Goor (2004), Effects of bit line coupling on the faulty behavior of DRAMs, In Proceedings 22nd IEEE VLSI test symposium p.1-6, IEEE .