Z Al-Ars, S Hamdioui, G Mueller, AJ van de Goor (2005), Framework for fault analysis and test generation in drams, s.n. (Eds.), In Proceedings of design, automation and test in Europe 2005 (DATE 05) p.100-105, IEEE.

S Hamdioui, Z Al-Ars, AJ van de Goor, R Wadsworth (2005), Impact of stresses on the fault coverage of memory tests, s.n. (Eds.), In Proceedings of the IEEE international workshop on memory technology, design and testing p.103-108, IEEE.

Z Al-Ars, S Hamdioui, AJ van de Goor (2004), Effects of bit line coupling on the faulty behavior of DRAMs, In Proceedings 22nd IEEE VLSI test symposium p.1-6, IEEE.

Z Al-Ars, M Herzog, I Schanstra, AJ van de Goor (2004), Influence of bit line twisting on the faulty behavior or DRAMs, FM Titsworth (Eds.), In Records of the 2004 International workshop on Memory Technology, Design and Testing MTDT 2004 p.32-37, IEEE.

S Hamdioui, Z Al-Ars, AJ van de Goor, M Rodgers (2004), Linked faults in random access memories: concept fault models, test algorithms, and industrial results, In IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems Volume 23 p.737-757.

Z Al-Ars, AJ van de Goor (2004), Soft faults and the importance of stresses in memory testing, G Gielen, J Figueras (Eds.), In Design, automation and test in Europe; Date04 Proceedings p.1084-1091, IEEE.

AJ van de Goor, S Hamdioui, Z Al-Ars (2004), Tests for address decoder delay faults in RAMs due to inter-gate opens, In Proceedings of the 9th IEEE European Test Symposium p.146-153, IEEE.

AJ van de Goor, S Hamdioui, Z Al-Ars (2004), The effectiveness of Scan test and its new variants, FM Titsworth (Eds.), In Records of the 2004 International workshop on Memory Technology, Design and Testing MTDT 2004 p.26-31, IEEE.

Z Al-Ars, S Hamdioui, AJ van de Goor (2003), A fault primitive based analysis of linked faults in RAMs, s.n. (Eds.), In MTDT 2003; Records of the 2003 international workshop on memory technology, design and testing p.33-39, IEEE.

Z Al-Ars, AJ van de Goor (2003), Analyzing the impact of process variations on DRAM testing using border resistance traces, s.n. (Eds.), In ATS 2003; proceedings of the twelfth Asian test symposium p.24-27, IEEE.