P Celinski, SD Cotofana, D Abbott (2002), Threshold logic parallel counters for 32-bit multipliers, s.n. (Eds.), In International symposium on smart materials, Nano-, and micro-smart systems 2002 p.205-214, SPIE.

M Sima, S Vassiliadis, JTJ van Eijndhoven, SD Cotofana (2002), Y'UV-to-R'G'B' color space conversion on FPGA-augmented TriMedia-32 processor, In Proceeding ProRISC 2002 p.465-471, Dutch Technology Foundation STW.

C Lageweg, SD Cotofana, S Vassiliadis (2001), A linear threshold gate implemantation in single electron technology, A Jacobs (Eds.), In Proceedings p.93-98, IEEE.

MD Padure, SD Cotofana, C Dan, M Bodea, S Vassiliadis (2001), A new latch-based threshold logic familiy, In CAS 2001: proceedings p.531-534, IEEE.

C Lageweg, SD Cotofana, S Vassiliadis (2001), A turnstile based single electron memory element, In SAFE 2001: proceedings p.103-108, STW Technology Foundation.

C Lageweg, SD Cotofana, S Vassiliadis (2001), Achieving fanout capabilities in single electron encoded logic networks, In Proceedings. Vol. 2 p.1383-1386, IEEE.

M Sima, SD Cotofana, JTJ van Eijndhoven, S Vassiliadis (2001), An 8-point IDCT computing resource implemented on a trimedia/CPU64 reconfigurable functional unit, F Karelse (Eds.), In Proceedings p.211-218, STW Technology Foundation.

D Crisu, SD Cotofana, S Vassiliadis (2001), An energy-aware architectural exploration tool for ARM-based SOCs, s.n..

D Crisu, SD Cotofana, S Vassiliadis (2001), An energy-aware architectural exploration tool for ARM-based SOCs, In ProRISC 2001: proceedings p.327-337, STW Technology Foundation.

E Panainte, I Athanasiu, SD Cotofana (2001), An optimization framework for retargetable compilers, I Dumitrache, C Buiu (Eds.), In CSCS-13: proceedings p.427-432, Editura Politehnica.