CR Lageweg, SD Cotofana, S Vassiliadis (2002), A family of single electron static buffered Boolean logic, In Proceedings of ProRISC 2002 p.339-343.

CR Lageweg, SD Cotofana, S Vassiliadis (2002), A full adder implementation using SET based linear threshold gates, A Baric, et al. (Eds.), In Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002 p.665-669.

D Crisu, SD Cotofana, S Vassiliadis (2002), A hardware/software co-simulation environment for graphics accelerator development in ARM-based SOCs, In Proceedings of ProRISC 2002 p.255-267.

MD Padure, SD Cotofana, S Vassiliadis, C Dan, M Bodea (2002), A low-power threshold logic family, In ICECS 2002; 9th IEEE International Conference on Electronica, Circuits and Systems p.657-660.

D Crisu, SD Cotofana, S Vassiliadis (2002), A proposal of a tile-based open GL compliant rasterization engine.

M Sima, SD Cotofana, S Vassiliadis, JTJ van Eijndhoven (2002), A reconfigurable functional unit for TriMedia/CPU64, EF Deprettere, J Teich, S Vassiliads (Eds.), In Embedded processor design challenges: Systems, Architectures, Modeling and Simulation - SAMOS p.224-242.

JSSM Wong, S Vassiliadis, SD Cotofana (2002), A sum of absolute differences implementation in FPGA hardware, M Fernandez (Eds.), In EUROMICRO 2002; Proceedings of the 28th EUROMICRO Conference p.183-188.

JSSM Wong, B Stougie, SD Cotofana (2002), Alternatives in FPGA-based SAD implementations, In 2002 IEEE international conference on field-programmable technology (FPT) p.449-452.

JSSM Wong, B Stougie, SD Cotofana (2002), An investigation on FPGA based SAD hardware implementations, In Proceedings of ProRISC 2002 p.567-573.

MD Padure, SD Cotofana, C Dan, S Vassiliadis, M Bodea (2002), Compact delay modeling of latch-based threshold logic gates, In CAS 2002 Proceedings, Volume 2 p.317-320.