C Hu, SD Cotofana, J Jiang (2004), Single-electron tunneling transistor implementation of periodic symmetric functions, In IEEE Transactions on Circuits and Systems Part 2: Analog and Digital Signal Processing Volume 51 p.593-597.

PT Stathis, S Vassiliadis, SD Cotofana (2003), A hierarchical sparse matrix storage format for vector processors, s.n. (Eds.), In IPDPS 2003; 17th international parallel and distributed processing symposium p.1-8, IEEE.

P Celinski, SD Cotofana, D Abbott (2003), A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder, J Mira, JR Álvarez (Eds.), In Computational methods in neural modeling; seventh international work-conference on artificial and natural networks, IWANN 2003 p.73-80, Springer.

P Celinski, D Abbott, SD Cotofana (2003), Area efficient, High speed parallel counter circuits using charge recycling threshold logic, In ISCAS 2003; Proceedings of the 2003 IEEE international symposium on circuits and systems p.233-236, IEEE.

CR Lageweg, SD Cotofana, S Vassiliadis (2003), Building blocks for electron counting arithmetic, s.n. (Eds.), In Proceedings of ProRISC 2003 p.222-228, STW.

MD Padure, SD Cotofana, S Vassiliadis (2003), CMOS implementation of generalized threshold functions, J Mira, JR Álvarez (Eds.), In Computatational methods in neural modeling: seventh international work-conference on artificial and natural neural networks, IWANN 2003 p.65-72, Springer.

M Sima, S Vassiliadis, SD Cotofana, JTJ van Eijndhoven (2003), Color space conversion for MPEG decoding on FPGA-augmented trimedia processor, E Deprettere, S Bhattacharyya, J Cavallaro, A Darte, L Thiele (Eds.), In ASAP 2003; Proceedings 2003, the IEEE international conference on application-specific systems, archtectures and processors p.250-259, IEEE.

T Niculiu, SD Cotofana (2003), Concurrent engineering for intelligent simulation, U Baake, J Herbst, I Graessler (Eds.), In ECEC 2003, tenth European concurrent engineering conference, tenth anniversary conference p.95-99, Eurosis.

PT Stathis, S Vassiliadis, SD Cotofana (2003), D-SAB: a sparse matrix benchmark suite, V Malyshkin (Eds.), In Parallel computing technologies; seventh international conference, PaCt 2003 p.549-554, Springer.

AM Molnos, MJM Heijligers, SD Cotofana, JTJ van Eijndhoven, SD Mesman (2003), Data cache optimization in multimedia applications, s.n. (Eds.), In Proceedings of ProRISC 2003 p.529-532, STW.