JY Hur, JSSM Wong, SD Cotofana (2004), Implementation of a dual analog decoder, In Proceedings of Pro-RISC 2004 p.1-8, Technology Foundation STW.

D Crisu, SD Cotofana, S Vassiliadis, P Liuha (2004), Logic-enhanced memory for 3D graphics tile-based rasterizers, In The 2004 47th Midwest symposium on Circuits and Systems p.237-240, IEEE.

P Celinski, S Al-Sarawi, D Abbott, SD Cotofana, S Vassiliadis (2004), Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/Threshold-logic approach, A Smailagic, M Bayoumi (Eds.), In Proceedings IEEE Computer Society annual symposium on VLSI; Emerging trends in VLSI systems design p.127-132, IEEE.

T Niculiu, A Manolescu, SD Cotofana (2004), Looking for intelligent reconfigurable simulation, C Bobeanu (Eds.), In Modelling and simulation 2004 p.5-12, Eurosis-ETI.

D Crisu, S Vassiliadis, SD Cotofana (2004), Low cost and latency embedded 3D graphics reciprocation, In Proceedings of 2004 IEEE international symposium on circuits and systems p.905-908, IEEE.

SD Cotofana, CR Lageweg, S Vassiliadis (2004), On effective computation with nanodevices: a single electron tunnelling technology case study, In CAS 2004 Proceedings 2004 International semiconductor conference p.41-50, IEEE.

M Sima, SD Cotofana, S Vassiliadis, JTJ van Eijndhoven, KA Vissers (2004), Pel reconstruction on FPGA-augmented TriMedia, In IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 12 p.622-635.

R Eggermont, SD Cotofana, CR Lageweg (2004), Profiling-based state assignment for low power dissipation, In Proceedings of Pro-RISC 2004 p.377-384, Technology Foundation STW.

J Cheng, C Hu, SD Cotofana, J Jiang (2004), SPICE Implementation of a compact single electron tunneling transistor model, In IEEE-NANO 2004 Proceedings p.1-4, IEEE.

CR Lageweg, SD Cotofana, S Vassiliadis (2004), Single electron encoded latches and flip-flops, In IEEE Transactions on Nanotechnology Volume 3 p.237-248.