L Huang, D Crisu, SD Cotofana (2004), Heuristic algorithms for primitive traversal acceleration in tile-based rasterization, In Proceedings of Pro-RISC 2004 p.408-414.

T Niculiu, SD Cotofana (2004), Hierarchical intelligent simulation, I Smit, W Wallach, GE Lasker (Eds.), In Cognitive, emotive and ethical aspects of decision making in humans and in artificial intelligence p.45-50.

T Niculiu, M Ciuc, SD Cotofana (2004), Hierarchical models for intelligent reconfigurable simulation, In Proceedings of the Fifteenth IASTED International Conference on Modelling and Simulation p.350-355, Acta Press.

T Niculiu, SD Cotofana (2004), Hierarchical templates for simulated intelligence, In EUROSIM- Simulation News Europe Volume 38/39 p.16-22.

T Niculiu, C Aktouf, SD Cotofana (2004), Hierarchical testability assisted intelligent simulation, In International Journal of Modelling & Simulation Volume 24 p.26-36.

D Crisu, SD Cotofana, S Vassiliadis, P Liuha (2004), High-level energy estimation for ARM-based SOCs, AD Pimentel, S Vassiliadis (Eds.), In Computer systems: architectures, modeling, and simulation p.168-177, Springer.

JY Hur, JSSM Wong, SD Cotofana (2004), Implementation of a dual analog decoder, In Proceedings of Pro-RISC 2004 p.1-8.

P Celinski, S Al-Sarawi, D Abbott, SD Cotofana, S Vassiliadis (2004), Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/Threshold-logic approach, A Smailagic, M Bayoumi (Eds.), In Proceedings IEEE Computer Society annual symposium on VLSI; Emerging trends in VLSI systems design p.127-132.

D Crisu, SD Cotofana, S Vassiliadis, P Liuha (2004), Logic-enhanced memory for 3D graphics tile-based rasterizers, In The 2004 47th Midwest symposium on Circuits and Systems p.237-240.

T Niculiu, A Manolescu, SD Cotofana (2004), Looking for intelligent reconfigurable simulation, C Bobeanu (Eds.), In Modelling and simulation 2004 p.5-12.