M Sima, SD Cotofana, S Vassiliadis, JTJ van Eijndhoven, K Vissers (2001), MPEG macroblock parsing and Pel reconstruction on an FPGA-augmented TriMedia processor, In 2001 IEEE International conference on Computer design: VLSI in computers & processors p.425-431.

T Niculiu, SD Cotofana (2001), Multi-hierarchical learning-based co-simulation, MH Hamza (Eds.), In Proceedings p.24-29.

T Niculiu, C Aktouf, SD Cotofana (2001), Multihierarchical intelligent simulation, In Polytechnical University of Bucharest. Scientific Bulletin. Series C: Electrical Engineering and Computer Science Volume 63 p.15-24.

S Vassiliadis, JSSM Wong, SD Cotofana (2001), Network processors: issues and prospectives, In PDPTA'2001: proceedings. Vol. 4 p.1827-1833.

JSSM Wong, S Vassiliadis, SD Cotofana (2001), SAD implementation in FPGA hardware, In ProRISC 2001: proceedings p.738-742.

C Lageweg, SD Cotofana, S Vassiliadis (2001), Single electron encoded logic circuits, In SAFE 2001: proceedings p.96-102.

P Stathis, SD Cotofana, S Vassiliadis (2001), Sparse matrix vector multiplication evaluation using the BBCS scheme, Y Manolopoulos, S Evripidou (Eds.), In Proceedings. Vol. 1 p.40-49.

S Vassiliadis, JSSM Wong, SD Cotofana (2001), The MOLEN þµ-coded processor, G Goos, ... [et Al] (Eds.), In Field-progammable logic and applications p.275-285.

P Stathis, S Vassiliadis, SD Cotofana (2001), Transposition mechanism for sparse matrices on vector processors, In ProRISC 2001: proceedings p.641-645.

M Sima, SD Cotofana, S Vassiliadis, JTJ van Eijndhoven (2001), Variable length decoder implemented on a TriMedia/CPU64 reconfigurable functional unit, In ProRISC 2001: proceedings p.605-610.