S Hamdioui, G. di Natale, G van Battum, J-L Danger, F Smailbegovic, M Tehranipoor (2014), Hacking and protecting IC hardware, W Nebel, G Fettweis (Eds.), In Proceedings of the 2014 International Conference on Design, Automation & Test in Europe p.1-7, EDAA.

M Taouil, M Masadeh, S Hamdioui, EJ Marinissen (2014), Interconnect test for 3D stacked memory-on-logic, W Nebel, G Fettweis (Eds.), In Proceedings of the 2014 International Conference on Design, Automation & Test in Europe p.1-6, EDAA.

Y Sfikas, YE Tsiatouhas, S Hamdioui (2014), Layout-based refined NPSF model for DRAM characterization and testing, In IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 22 p.1446-1450.

PD Joshi, S Hamdioui (2014), Line graph based fast rerouting and reconfiguration for handling transient and permanent node failures, L Trajkovic, A Jajszczyk (Eds.), In Proceedings - 2014 IEEE 15th International Conference on High Performance Switching and Routing p.167-172, IEEE Society.

S Hamdioui, H Aziza, GC Sirakoulis (2014), Memristor based memories: Technology, design and test, I Voyatzis (Eds.), In Proceedings - 9th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era p.1-7, IEEE Society.

M Taouil, S Hamdioui, EJ Marinissen (2014), Quality versus cost analysis for 3D Stacked ICs, C Thibeault (Eds.), In Proceedings - 32nd IEEE VLSI Test Symposium p.1-6, IEEE.

PD Joshi, A Sen, S Hamdioui, K Bertels (2014), Region disjoint paths in a class of optimal line graph networks, D El Baz, X Liu, CH Hsu, K Kang, W Chen (Eds.), In Proceedings - 17th IEEE International Conference on Computational Science and Engineering (CSE 2014) p.1256-1260, IEEE.

PD Joshi, S Hamdioui (2014), Security methods in fault tolerant modified line graph based networks, M Ottavi, S Hamdioui (Eds.), In Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) p.57-62, IEEE Society.

PD Joshi, S Hamdioui (2014), Shortest path reduction in a class of uniform fault tolerant networks, M Ottavi, S Hamdioui (Eds.), In Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) p.234-239, IEEE Society.

AMMO Cortez, G Roelofs, S Hamdioui, G. di Natale (2014), Testing PUF-based secure key storage circuits, G Fettweis, W Nebel (Eds.), In Proceedings of the 2014 International Conference on Design, Automation & Test in Europe p.1-6, EDAA.