MSK Seyab, S Hamdioui (2012), Analyzing combined impacts of parameter variations and BTI in nano-scale logical gates, s.n. (Eds.), In 1st Workshop on manufacturable and dependable multicore architectures at nanoscale p.1-5, s.n..

MSK Seyab, S Hamdioui, H Kukner, F Catthoor, P Raghavan (2012), BTI Impacts on logical gates in nano-scale CMOS technology, s.n. (Eds.), In 15th IEEE Symposium on design and diagnostics of electronic circuits and systems p.1-6, IEEE Society.

MSK Seyab, S Hamdioui, F Catthoor (2012), Comparative BTI analysis in nano-scale circuits lifetime, s.n. (Eds.), In 4th Workshop on design for reliability p.1-8, s.n..

NZB Haron, S Hamdioui (2012), DfT schemes for resistive open defects in RRAMs, s.n. (Eds.), In Design, automation & test in Europe conference & exhibition p.1-6, s.n..

M Taouil, M Lefter, S Hamdioui (2012), Exploring test opportunities for memory and interconnects in 3D ICs, s.n. (Eds.), In International design & test symposium p.1-6, s.n..

MSK Seyab, S Hamdioui, M Taouil, H Kukner, P Raghavan, F Catthoor (2012), Impact of partial resistive defects and bias temperature instability on SRAM decoder reliablity, s.n. (Eds.), In International design & test symposium p.1-6, s.n..

MSK Seyab, S Hamdioui, H Kukner, P Raghavan, F Catthoor (2012), Incorporating Parameter Variations in BTI Impact on Nano-scale Logical Gates Analysis, s.n. (Eds.), In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems p.1-6, IEEE Society.

AM Monteiro OliveiraCortez, A Dargar, GJ Schrijen, S Hamdioui (2012), Modeling SRAM Start-Up Behavior for Physical Unclonable Functions, s.n. (Eds.), In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems p.1-6, IEEE Society.

M Taouil, S Hamdioui (2012), On Optimizing Test Cost for Wafer-to-Wafer 3D Stacked ICs, s.n. (Eds.), In 7th International conference on design & technology of integrated systems in nanoscale era p.1-6, s.n..

M Taouil, S Hamdioui (2012), Yield improvement for 3D wafer-to-wafer stacked memories, In Journal of Electronic Testing: theory and applications Volume 28 p.523-534.