Anteneh Gebregiorgis, Fabian Oboril, Mehdi B. Tahoori, Said Hamdioui (2016), Instruction cache aging mitigation through Instruction Set Encoding, Peter Wright, Saibal Mukhopadhyay, Brian Cline (Eds.), In Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016 p.325-330, IEEE.

Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels, Mohammad Alfailakawi (2016), Non-Volatile Look-up Table Based FPGA Implementations, Rached Tourki (Eds.), In Proceedings , IEEE.

Adib Haron, Jintao Yu, Razvan Nane, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels (2016), Parallel Matrix Multiplication on Memristor-Based Computation-in-Memory Architecture, In 2016 International Conference on High Performance Computing & Simulation (HPCS) p.759-766, IEEE.

Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor, Wim Dehaene (2016), Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability, Baris Taskin, Prasun Ghosal (Eds.), In Proceedings - IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016) p.725-730, IEEE.

Peyman Pouyan, Esteve Amat, Said Hamdioui, Antonio Rubio (2016), RRAM Variability and its Mitigation Schemes, In 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 p.141-146, IEEE.

Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Franky Catthoor, Wim Dehaene (2016), Read Path Degradation Analysis in SRAM, In Proceedings - 21st IEEE European Test Symposium, ETS 2016 p.1-2, IEEE.

Jintao Yu, Razvan Nane, Adib Haron, Said Hamdioui, H Corporaal, Koen Bertels (2016), Skeleton-based design and simulation flow for Computation-in-Memory architectures, W. Zhao, C.A. Moritz (Eds.), In 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) p.165-170, Association for Computing Machinery (ACM).

Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels (2016), Synthesizing HDL to Memristor Technology: A Generic Framework, W. Zhao, C.A. Moritz (Eds.), In 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) p.43-48, Association for Computing Machinery (ACM).

S Hamdioui, M Taouil, NZB Haron (2016), Testing open defects in memristor-based memories, In IEEE Transactions on Computers Volume 64 p.247-259.

C Papameletis, B Keller, V Chickermane, S Hamdioui, EJ Marinissen (2015), A DfT architecture and tool flow for 3-D SICs with test data compression, embedded cores, and multiple towers, In IEEE Design & Test Volume 32 p.40-48.