M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik (2013), Using 3D-COSTAR for 2.5D test cost optimization, s.n. (Eds.), In IEEE International 3D Systems Integration Conference p.1-8, IEEE.

L Petrica, V Codreanu, SD Cotofana (2013), VASILE: a reconfigurable vector architecture for instruction level frequency scaling, s.n. (Eds.), In 12th IEEE low voltage low power conference p.1-4, IEEE.

MSK Seyab, S Hamdioui (2013), Variability and reliability analyses in SRAM decoder, s.n. (Eds.), In 4th Workshop on design for reliability p.1-8, s.n..

KGW Goossens, AP Pereira de Azevedo Filho, K Chandrasekar, D Mirzoyan, AM Molnos, A Beyranvand Nejad, AT Nelson (2013), Virtual execution platforms for mixed-time-criticality systems: The CompSOC architecture and design flow, In SIGBED Review Volume 10 p.23-34.

M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik (2012), 3D-COSTAR: a cost model for 3D stacked ICs, Y Zorian, E Marijnissen, S Hamdioui (Eds.), In Proceedings Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits p.1-6, IEEE.

GR Voicu, M Enachescu, SD Cotofana (2012), A 3D stacked high performance scalable architecture for 3D fourier transform, s.n. (Eds.), In 30th IEEE international conference on computer design p.1-2, IEEE.

N Cucu Laurenciu, SD Cotofana (2012), A Markovian, variation-aware circuit-level aging model, s.n. (Eds.), In International symposium on nanoscale architectures p.1-7, IEEE.

P Pham Quoc Cuong, Z Al-Ars, KLM Bertels (2012), A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems, s.n. (Eds.), In Conference on ReConFigurable computing and FPGAs p.1-6, s.n..

R Nane, VM Sima, KLM Bertels (2012), A lightweight speculative and predicative scheme for hardware execution, s.n. (Eds.), In International conference on ReConFigurable computing and FPGAs p.1-6, IEEE.

C Chen, Ye Lu (2012), A novel flit serialization strategy to utilize partially faulty links in networks-on-chip, s.n. (Eds.), In 2012 Sixth IEEE/ACM international symposium on networks-on-chip p.1-8, IEEE.