L. Lao, B. van Wee, Imran Ashraf, J. van Someren, N. Khammassi, K. Bertels, C.G. Almudever (2019), Mapping of Lattice Surgery-based Quantum Circuits on Surface Code Architectures, In Quantum Science and Technology Volume 4 p.1-20.
Muath Abu Lebdeh, Uljana Reinsalu, Hoang Anh Du Nguyen, Stephan Wong, Said Hamdioui (2019), Memristive Device Based Circuits for Computation-in-Memory Architectures, In 2019 IEEE International Symposium on Circuits and Systems (ISCAS) p.1-5.
Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor (2019), Methodology for Application-Dependent Degradation Analysis of Memory Timing, In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) p.162-167.
Helmi Helmiriawan, Zaid Al-Ars (2019), Multi-target Regression Approach for Predictive Maintenance in Oil Refineries using Deep Learning, In International Journal of Neural Networks and Advanced Applications Volume 6 p.18-24.
Ambika Prasad Shah, Santosh Kumar Vishvakarma, Sorin Cotofana (2019), NBTI stress delay sensitivity analysis of reliability enhanced Schmitt trigger based circuits, In Microelectronics Reliability Volume 102 p.1-8.
Y. Jiang, N. Cucu Laurenciu, S. D. Cotofana (2019), Non-Equilibrium Green Function-based Verilog-A Graphene Nanoribbon Model, Aidan Quinn, Guangyong Li, Wen Li, Alan Mathewson (Eds.), In 18th International Conference on Nanotechnology, NANO 2018 p.1-4.
Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Dan Cotofana (2019), On Basic Boolean Function Graphene Nanoribbon Conductance Mapping, In IEEE Transactions on Circuits and Systems I: Regular Papers Volume 66 p.1948-1959.
Ernst Houtgast (2019), On Hardware-Accelerated Maximally-Efficient Systolic Arrays: Acceleration and Optimization of Genomics Pipelines Through Hardware/Software Co-Design, PhD Thesis Delft University of Technology.
Daniƫl Kraak, Mottagiallah Taouil, Innocent Agbo, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor (2019), Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM, In IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 27 p.1308-1321.
Lizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar (2019), Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing, In 2019 IEEE European Test Symposium (ETS) p.1-6.