MJ Schulte, L Marquette, S Krithivasan, EG Walters, CJ Glossner (2003), Combined multiplication and sum-of-squares units, E Deprettere, S Bhattacharyya, J Cavallaro, A Darte, L Thiele (Eds.), In ASAP 2003; Proceedings 2003, the IEEE international conference on application-specific systems, archtectures and processors p.204-215.

E Panainte, KLM Bertels, S Vassiliadis (2003), Compiling for the molen programming paradigm, PYK Cheung, GA Constantinides, JT de Sousa (Eds.), In Field-programmable logic and applications; 13th international conference, FPL 2003 p.900-910, Springer.

E Panainte, KLM Bertels, S Vassiliadis (2003), Compiling for the molen programming paradigm, s.n. (Eds.), In PA3CT; Program acceleration through application and architecture driven code transformations Symposium Proceedings p.41-43.

H Calderón, S Vassiliadis (2003), Computer graphics and the MOLEN paradigm: a survey, s.n. (Eds.), In Proceedings of ProRISC 2003 p.23-36.

T Niculiu, SD Cotofana (2003), Concurrent engineering for intelligent simulation, U Baake, J Herbst, I Graessler (Eds.), In ECEC 2003, tenth European concurrent engineering conference, tenth anniversary conference p.95-99.

I Schanstra, AJ van de Goor (2003), Consequences of RAM bitline twisting for test coverage, N Wehn, D Verkest (Eds.), In DATE'03; design automation and test in Europe p.1176-1177.

AM Molnos, MJM Heijligers, SD Cotofana, JTJ van Eijndhoven, SD Mesman (2003), Data cache optimization in multimedia applications, s.n. (Eds.), In Proceedings of ProRISC 2003 p.529-532.

MD Padure, SD Cotofana, S Vassiliadis (2003), Design and experimental results of a CMOS flip-flop featuring embedded threshold logic, In ISCAS 2003; Proceedings of the 2003 IEEE international symposium on circuits and systems p.253-256.

D Crisu, SD Cotofana, S Vassiliadis (2003), Design tradeoffs for an embedded open GL-compliant hardware rasterizer, In Proceedings of ProRISC 2003 p.49-55.

S Hamdioui, AJ van de Goor, M Rodgers (2003), Detecting intra-word faults in word-oriented memories, s.n. (Eds.), In 21th IEEE VLSI test symposium p.241-247.