GK Kuzmanov, GN Gaydadjiev, S Vassiliadis (2004), Loading pµ-code: design considerations, AD Pimentel, S Vassiliadis (Eds.), In Computer systems: architectures, modeling, and simulation p.11-19, Springer.

Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis (2004), Loading ρμ-code: Design considerations, Andy D. Pimentel, Stamatis Vassiliadis (Eds.), In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) p.11-19, Springer.

P Celinski, S Al-Sarawi, D Abbott, SD Cotofana, S Vassiliadis (2004), Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/Threshold-logic approach, A Smailagic, M Bayoumi (Eds.), In Proceedings IEEE Computer Society annual symposium on VLSI; Emerging trends in VLSI systems design p.127-132.

D Crisu, SD Cotofana, S Vassiliadis, P Liuha (2004), Logic-enhanced memory for 3D graphics tile-based rasterizers, In The 2004 47th Midwest symposium on Circuits and Systems p.237-240.

T Niculiu, A Manolescu, SD Cotofana (2004), Looking for intelligent reconfigurable simulation, C Bobeanu (Eds.), In Modelling and simulation 2004 p.5-12.

D Crisu, S Vassiliadis, SD Cotofana (2004), Low cost and latency embedded 3D graphics reciprocation, In Proceedings of 2004 IEEE international symposium on circuits and systems p.905-908.

D Iancu, CJ Glossner, M Moudgill (2004), Low delay spread multi-path cancellation for 3G WCDMA, M Aleksy, Bhagyavati, S Byrne, KE Corey, et al (Eds.), In Proceedings of the winter international symposium on Information and communication technologies p.428-433.

B Pourebrahimi, K Bertels, S Vassiliadis, K Sigdel (2004), Matchmaking within multi-agent systems, In Proceedings of Pro-RISC 2004 p.118-124.

I Antochi, BHH Juurlink, S Vassiliadis, P Liuha (2004), Memory bandwidth requirements of tile-based rendering, AD Pimentel, S Vassiliadis (Eds.), In Computer systems: architectures, modeling, and simulation p.323-332, Springer.

S Hamdioui, R Wadsworth, J delos Reyes (2004), Memory fault modeling trends: a case study, In Journal of Electronic Testing: theory and applications Volume 20 p.245-255.