T Niculiu, SD Cotofana (2003), Hierarchical simulated reconfigurable intelligence templates, MH Hamza (Eds.), In Proceedings of the IASTED international conference on intelligent systems and control p.39-44, ACTA Press.

D Crisu, SD Cotofana, S Vassiliadis (2003), High-level energy estimation for ARM-based SOCs, s.n. (Eds.), In Third international workshop on systems, architectures, modeling, and simulation p.148-153, SAMOS Initiative.

M Sima, S Vassiliadis, SD Cotofana, JTJ van Eijndhoven (2003), Inverse quantization on FPGA-augmented trimedia, s.n. (Eds.), In Proceedings of ProRISC 2003 p.153-157, STW.

P Celinski, SD Cotofana, D Abbott (2003), Logical effort delay modeling of sense amplifier based charge recycling threshold logic gates, s.n. (Eds.), In Proceedings of ProRISC 2003 p.43-48, STW.

S Vassiliadis, JSSM Wong, SD Cotofana (2003), Microcode processing: positioning and directions, In IEEE Micro Volume 23 p.21-30.

SD Cotofana, CR Lageweg, S Vassiliadis (2003), On computing addition related arithmetic operations via controlled transport of charge, J Bajard, M Schulte (Eds.), In ARITH-16 2003; 16th IEEE symposium on computer arithmetic p.245-252, IEEE Society.

CR Lageweg, SD Cotofana, S Vassiliadis (2003), Single electron encoded SET memory elements, s.n. (Eds.), In Proceedings of ProRISC 2003 p.214-221, STW.

CR Lageweg, SD Cotofana, S Vassiliadis (2003), Single electron encoded logic memory elements, s.n. (Eds.), In IEEE-NON 2003; 2003 Third IEEE conference on nantechnology p.1-4, IEEE Society.

P Celinski, SD Cotofana, JF López, S Al-Sarawi, D Abbott (2003), State-of-the-art in CMOS threshold-logic VSLI gate implementations and applications, s.n. (Eds.), In Microtechnologies for the new millenium 2003 p.53-64, SPIE.

CR Lageweg, SD Cotofana, S Vassiliadis (2002), 7/3 and 7/2 Counters implemented in single electron technology, In Proceedings of ProRISC 2002 p.344-350, Dutch Technology Foundation STW.