MD Padure, SD Cotofana, S Vassiliadis (2002), High-speed hybrid threshold-boolean logic counters and compressors, s.n. (Eds.), In MWSCAS-2002; proceedings of the 2002 45th Midwest symposium on circuits and systems p.457-460, IEEE Society.

M Sima, SD Cotofana, S Vassiliadis, JTJ van Eijndhoven, K Vissers (2002), MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU64, J Arnold, L Pocek (Eds.), In IEEE Symposium on field-programmable custom computing machines p.261-273, IEEE Society.

JSSM Wong, S Vassiliadis, SD Cotofana (2002), Microcoded reconfigurable embedded processors: current developments, EF Deprettere, J Teich, S Vassiliadis (Eds.), In Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS p.207-224, Springer.

JSSM Wong, SD Cotofana (2002), On teaching embedded systems design to electrical engineering students, K Fernstrom (Eds.), In 3rd International conference on information communication technologies in education p.505-515, National and Kapodistrian University of Athens.

CR Lageweg, SD Cotofana, S Vassiliadis (2002), Static buffered SET based logic gates, In IEEE-NANO 2002; Proceedings of the 2002 2nd IEEE Conference on Nanotechnology p.491-494, IEEE Society.

JSSM Wong, G Luo, SD Cotofana (2002), Synthetic benchmark generator for the MOLEN processor, In Proceedings of ProRISC 2002 p.561-567, Dutch Technology Foundation STW.

P Celinski, SD Cotofana, D Abbott (2002), Threshold logic parallel counters for 32-bit multipliers, s.n. (Eds.), In International symposium on smart materials, Nano-, and micro-smart systems 2002 p.205-214, SPIE.

M Sima, S Vassiliadis, JTJ van Eijndhoven, SD Cotofana (2002), Y'UV-to-R'G'B' color space conversion on FPGA-augmented TriMedia-32 processor, In Proceeding ProRISC 2002 p.465-471, Dutch Technology Foundation STW.

C Lageweg, SD Cotofana, S Vassiliadis (2001), A linear threshold gate implemantation in single electron technology, A Jacobs (Eds.), In Proceedings p.93-98, IEEE .

MD Padure, SD Cotofana, C Dan, M Bodea, S Vassiliadis (2001), A new latch-based threshold logic familiy, In CAS 2001: proceedings p.531-534, IEEE Society.