P Celinski, D Abbott, SD Cotofana (2003), Area efficient, High speed parallel counter circuits using charge recycling threshold logic, In ISCAS 2003; Proceedings of the 2003 IEEE international symposium on circuits and systems p.233-236, IEEE Society.

CR Lageweg, SD Cotofana, S Vassiliadis (2003), Building blocks for electron counting arithmetic, s.n. (Eds.), In Proceedings of ProRISC 2003 p.222-228, STW.

MD Padure, SD Cotofana, S Vassiliadis (2003), CMOS implementation of generalized threshold functions, J Mira, JR Álvarez (Eds.), In Computatational methods in neural modeling: seventh international work-conference on artificial and natural neural networks, IWANN 2003 p.65-72, Springer.

M Sima, S Vassiliadis, SD Cotofana, JTJ van Eijndhoven (2003), Color space conversion for MPEG decoding on FPGA-augmented trimedia processor, E Deprettere, S Bhattacharyya, J Cavallaro, A Darte, L Thiele (Eds.), In ASAP 2003; Proceedings 2003, the IEEE international conference on application-specific systems, archtectures and processors p.250-259, IEEE Society.

T Niculiu, SD Cotofana (2003), Concurrent engineering for intelligent simulation, U Baake, J Herbst, I Graessler (Eds.), In ECEC 2003, tenth European concurrent engineering conference, tenth anniversary conference p.95-99, Eurosis.

PT Stathis, S Vassiliadis, SD Cotofana (2003), D-SAB: a sparse matrix benchmark suite, V Malyshkin (Eds.), In Parallel computing technologies; seventh international conference, PaCt 2003 p.549-554, Springer.

AM Molnos, MJM Heijligers, SD Cotofana, JTJ van Eijndhoven, SD Mesman (2003), Data cache optimization in multimedia applications, s.n. (Eds.), In Proceedings of ProRISC 2003 p.529-532, STW.

MD Padure, SD Cotofana, S Vassiliadis (2003), Design and experimental results of a CMOS flip-flop featuring embedded threshold logic, In ISCAS 2003; Proceedings of the 2003 IEEE international symposium on circuits and systems p.253-256, IEEE Society.

D Crisu, SD Cotofana, S Vassiliadis (2003), Design tradeoffs for an embedded open GL-compliant hardware rasterizer, In Proceedings of ProRISC 2003 p.49-55, STW.

CR Lageweg, SD Cotofana, S Vassiliadis (2003), Evaluation methodology for single electron encoded threshold logic gates, M Glesner, R Reis, H Eveking, V Mooney, L Indrusiak, P Zipf (Eds.), In VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip p.258-262, Technische Universität Darmstadt.