R Giorgi, Z Popovic, N Puzovic, AP Pereira de Azevedo Filho, B Juurlink (2008), Analyzing scalability of deblocking filter of H.264 via TLP exploitation in a new many-core architecture, L Fanucci (Eds.), In 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools p.189-194.
F Martorell, SD Cotofana, A Rubio (2008), An analysis of internal parameter variations effects on nanoscaled gates, In IEEE Transactions on Nanotechnology Volume 7 p.24-33.
M Ahmadi, S Wong (2008), An approach for optimal bandwidth allocation in packet processing systems, s.n. (Eds.), In CNSR 2008 conference p.208-214.
Y Lu, TM Thomas, GN Gaydadjiev, K Bertels (2008), An efficient algorithm for free resources management on the FPGA, s.n. (Eds.), In DATE '08 p.1095-1098.
KA Gbolagade, SD Cotofana (2008), An efficient RNS to binary converter using the moduli set {2n+1, 2n, 2n-1}, s.n. (Eds.), In Conference on Design of Circuits and Integrated Systems p.1-6.
L Hasan, Z Al-Ars, Z Nawaz (2008), A novel approach for accelerating the Smith-Waterman algorithm using recursive variable expansion, s.n. (Eds.), In 19th Annual Workshop on Circuits, Systems and Signal Processing p.40-45.
LL Mhamdi (2008), A partially buffered crossbar packet switching architecture and its scheduling, s.n. (Eds.), In IEEE Intl. Symposium on Computers and Communications p.1-7.
A Hansson, M Wiggers, A Moonen, KGW Goossens, M Bekooij (2008), Applying dataflow analysis to dimension buffers for guaranteed performance in networks on chip, s.n. (Eds.), In Second ACM/IEEE International Symposium on Networks-on- Chip p.211-212.
F Bouwens, M Berekovic, B de Sutter, GN Gaydadjiev (2008), Architecture enhancements for the ADRES coarse-grained reconfigurable array, In Lecture Notes in Computer Science Volume LNCS4917 p.66-81.
KA Gbolagade, SD Cotofana (2008), A residue to binary converter for the {2N+2, 2N+1, 2N} moduli set, s.n. (Eds.), In Forty-second Asilomar conference on signals, systems, and computers p.1785-1789.