D Theodoropoulos, GK Kuzmanov, GN Gaydadjiev (2010), A 3D-audio reconfigurable processor, s.n. (Eds.), In Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays p.107-110, Association for Computing Machinery (ACM).

Y Lu, TM Thomas, K Bertels, GN Gaydadjiev (2010), A communication aware online task scheduling algorithm for FPGA-based partially reconfigurable systems, R Sass, R Tessier (Eds.), In 18th IEEE Field-programmable custom computing machines p.65-68, IEEE.

D Theodoropoulos, GK Kuzmanov, GN Gaydadjiev (2010), A minimalistic for reconfigurable WFS-based immersive-audio, s.n. (Eds.), In 2010 Intl. conf. on reconfigurable computing p.1-6, IEEE.

TM Thomas, D Theodoropoulos, KLM Bertels, GN Gaydadjiev (2010), A novel HDL coding style to reduce power consumption for reconfigurable devices, s.n. (Eds.), In Proc. 2010 Intl. conf. on field-programmable technology p.295-299, IEEE.

TM Thomas, JY Hur, K Bertels, GN Gaydadjiev (2010), A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices, s.n. (Eds.), In 2010 IEEE 8th symp. on application specific processors p.105-110, IEEE.

CB Ciobanu, GK Kuzmanov, GN Gaydadjiev, A Ramirez (2010), A polymorphic register file for matrix operations, s.n. (Eds.), In 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation p.241-249, IEEE.

R Amini, EKA Gill, GN Gaydadjiev (2010), An attitude determination system suitable for a spacecraft.

A van den Berg, P Ren, E Marinissen, GN Gaydadjiev, KGW Goossens (2010), Badwidth analysis of functional interconnects used as test access mechanism, In Journal of Electronic Testing: theory and applications Volume 26 p.453-464.

Luigi Carro, Georgi N. Gaydadjiev (2010), Challenges for embedded multicore architecture, In CASES'10 p.259-260, Association for Computing Machinery (ACM).

D Ludovici, F Gilabert, GN Gaydadjiev, D Bertozzi (2010), Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology, s.n. (Eds.), In 3rd Intl. workshop on network on chip architectures p.37-42, IEEE.