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P Celinski, SD Cotofana, D Abbott (2003), A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder, J Mira, JR Álvarez (Eds.), In Computational methods in neural modeling; seventh international work-conference on artificial and natural networks, IWANN 2003 p.73-80, Springer.

P Celinski, D Abbott, SD Cotofana (2003), Area efficient, High speed parallel counter circuits using charge recycling threshold logic, In ISCAS 2003; Proceedings of the 2003 IEEE international symposium on circuits and systems p.233-236, IEEE.

E Schrik, AJ van Genderen, NP van der Meijs (2003), Coherent interconnect/substrate modeling using SPACE - an experimental study, J Franca, P Freitas (Eds.), In ESSDERC 2003 33rd European solid-state device research conference p.585-588, IEEE.

P Celinski, SD Cotofana, D Abbott (2003), Logical effort delay modeling of sense amplifier based charge recycling threshold logic gates, s.n. (Eds.), In Proceedings of ProRISC 2003 p.43-48, STW.

P Celinski, SD Cotofana, JF López, S Al-Sarawi, D Abbott (2003), State-of-the-art in CMOS threshold-logic VSLI gate implementations and applications, s.n. (Eds.), In Microtechnologies for the new millenium 2003 p.53-64, SPIE.

P Celinski, SD Cotofana, D Abbott (2002), Threshold logic parallel counters for 32-bit multipliers, s.n. (Eds.), In International symposium on smart materials, Nano-, and micro-smart systems 2002 p.205-214, SPIE.

E Schrik, AJ van Genderen, NP van der Meijs (2001), Combined BEM/FEM resistance modeling of straified substrates with layout-dependent doping patterns in the top layer, In SAFE - ProRISC - SeSens 2001: proceedings CD-ROM p.598-604, STW Technology Foundation.

AJ van Genderen, NP van der Meijs, E Schrik (2001), Modeling capacitive coupling effects via the substrate, In SAFE - ProRISC - SeSens proceedings: CD-ROM p.366-370, STW Technology Foundation.