AC Schneider Beck, MB Rutzig, GN Gaydadjiev, L Carro (2008), Transparent reconfigurable acceleration for heterogeneous embedded applications, s.n. (Eds.), In DATE '08 p.1208-1213, Kathy Preas. KP publications.

M Pericas, R Chaves Fernandes, GN Gaydadjiev, S Vassiliadis, M Valero (2008), Vectorized AES core for high-throughput secure environments, In Lecture Notes in Computer Science Volume 5336 p.83-94.

Y Lu, TM Thomas, GN Gaydadjiev, K Bertels (2007), A new model of placement quality measurement for online task placement, s.n. (Eds.), In Annual Workshop on Circuits, Systems and Signal Processing p.307-310, STW.

RJ Meeuws, YD Yankova, K Bertels, GN Gaydadjiev, S Vassiliadis (2007), A quantative prediction model for hardware/software partitioning, Najjar, W. Van Genderen, A Bertels, K. (Eds.), In 2007 International conference on field programmable logic and applications p.735-739, IEEE Society.

Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis (2007), A quantitative prediction model for hardware/software partitioning, In Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL p.735-739.

F Bouwens, M Berekovic, A Kanstein, GN Gaydadjiev (2007), Architectural Exploration of the ADRES coarse-grained reconfigurable array, Eduardo Marquez Koen Bertels Pedro C. Diniz, J. M. P. Cardoso (Eds.), In Reconfigurable Computing: Architectures, Tools and Applications p.1-13, Springer.

CB Ciobanu, B Spinean, GK Kuzmanov, GN Gaydadjiev (2007), Customized vector instruction set architecture, s.n. (Eds.), In Annual Workshop on Circuits, Systems and Signal Processing p.128-137, STW.

YD Yankova, K Bertels, GK Kuzmanov, GN Gaydadjiev, Y Lu, S Vassiliadis (2007), DWARV: Delftworkbench automated reconfigurable VHDL generator, Najjar, W. Van Genderen, A Bertels, K. (Eds.), In 2007 International conference on field programmable logic and applications p.697-701, IEEE Society.

B Spinean, CB Ciobanu, GK Kuzmanov, GN Gaydadjiev (2007), Design considerations for a domain specific vector microarchitecture, s.n. (Eds.), In Annual Workshop on Circuits, Systems and Signal Processing p.178-184, STW.

K Bertels, GK Kuzmanov, E Panainte, GN Gaydadjiev, YD Yankova, VM Sima, K Sigdel, RJ Meeuws, S Vassiliadis (2007), HaRTES toolchain early evaluation: profiling, compilation and HDL generation, Najjar, W. Van Genderen, A Bertels, K. (Eds.), In 2007 International conference on field programmable logic and applications p.402-408, IEEE Society.