F Campos Soares Borrego, S Wong (2007), Analysis of a user-space device-driver for the memcpy hardware, s.n. (Eds.), In Annual Workshop on Circuits, Systems and Signal Processing p.138-143.

M Ahmadi, SA Ostadzadeh, S Wong (2007), An analysis of rule-set databases in packet classification, s.n. (Eds.), In Annual Workshop on Circuits, Systems and Signal Processing p.110-115.

B Breijer, F Campos Soares Borrego, S Wong (2007), An OCM based shared memory controller for virtex 4, Najjar, W. Van Genderen, A Bertels, K. (Eds.), In 2007 International conference on field programmable logic and applications p.692-696.

M Ahmadi, S Wong (2007), A performance model for network processor architectures in packet processing system, Zheng SQ (Eds.), In 19th IASTED Parallel and distributed computing and systems p.1-6, Acta Press.

R Guo, JG Delgado-Frias, S Wong (2007), Cache replacement policies for IP address lookups, Delgado-Frias, J. G. (Eds.), In 5th IASTEDintl. conf. on Circuits, Signals, and Systems p.70-75, Acta Press.

JY Hur, TP Stefanov, S Wong, S Vassiliadis (2007), Customizing reconfigurable on-chip crossbar scheduler, s.n. (Eds.), In IEEE18th international conference Application-specific systems, architectures and processors p.210-215.

M Ahmadi, S Wong (2007), Hashing functions performance in packet classification, s.n. (Eds.), In Proceeding of the 2nd International conference on the latest advances in networks p.1-5.

JY Hur, S Wong, S Vassiliadis (2007), Partially reconfigurable point-to-point interconnects in virtex-II pro FPGAs, Eduardo Marquez Koen Bertels Pedro C. Diniz, J. M. P. Cardoso (Eds.), In Reconfigurable Computing: Architectures, Tools and Applications p.49-60, Springer.

S. Raaijmakers, S Wong (2007), Run-time partial reconfiguration for removal, placement and routing on the virtex-II-pro, Najjar, W. Van Genderen, A Bertels, K. (Eds.), In 2007 International conference on field programmable logic and applications p.679-683.

F Campos Soares Borrego, B Breijer, S Wong (2007), Supporting the linux operating system on the MOLEN processor prototype, s.n. (Eds.), In Annual Workshop on Circuits, Systems and Signal Processing p.205-210.