Y Sfikas, YE Tsiatouhas, M Taouil, S Hamdioui (2015), On resistive open defect detection in DRAMs: The charge accumulation effect, L Miclea, P Prinetto (Eds.), In Proceedings - 20th IEEE European Test Symposium p.1-6, IEEE.

M Taouil, S Hamdioui (2015), Post-bond interconnect test and diagnosis for 3-D memory stacked on logic, In IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems Volume 34 p.1860-1872.

M Taouil, S Hamdioui, EJ Marinissen (2015), Yield Improvement for 3D wafer-to-wafer stacked ICs using wafer matching, In ACM Transactions on Design Automation of Electronic Systems Volume 20 p.1-23.

EJ Marinissen, B De Wachter, K Smith, J Kiesewetter, M Taouil, S Hamdioui (2014), Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface, M Purtell, S Mitra (Eds.), In Proceedings 2014 IEEE International Test Conference p.1-10, ITC & IEEE.

M Taouil, M Masadeh, S Hamdioui, EJ Marinissen (2014), Interconnect test for 3D stacked memory-on-logic, W Nebel, G Fettweis (Eds.), In Proceedings of the 2014 International Conference on Design, Automation & Test in Europe p.1-6, EDAA.

M Taouil, S Hamdioui, EJ Marinissen (2014), Quality versus cost analysis for 3D Stacked ICs, C Thibeault (Eds.), In Proceedings - 32nd IEEE VLSI Test Symposium p.1-6, IEEE.

M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik (2013), Impact of mid-bond testing in 3D stacked ICs, s.n. (Eds.), In 16th IEEE Symposium on defect and fault tolerance in VLSI and nanotechnology systems p.1-6, IEEE.

M Lefter, GR Voicu, M Taouil, M Enachescu, S Hamdioui, SD Cotofana (2013), Is TSV-based 3D integration suitable for inter-die memory repair?, s.n. (Eds.), In Design, automation & test in Europe conference & exhibition p.1-4, IEEE.

M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik (2013), Using 3D-COSTAR for 2.5D test cost optimization, s.n. (Eds.), In IEEE International 3D Systems Integration Conference p.1-8, IEEE.

M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik (2012), 3D-COSTAR: a cost model for 3D stacked ICs, Y Zorian, E Marijnissen, S Hamdioui (Eds.), In Proceedings Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits p.1-6, IEEE.