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M Taouil, S Hamdioui (2012), Yield improvement for 3D wafer-to-wafer stacked memories, In Journal of Electronic Testing: theory and applications Volume 28 p.523-534.

M Taouil, S Hamdioui, E Marinissen (2011), How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs?, I Voyiatzis, H-J Wunderlich (Eds.), In 6th International conference on Design & Technology of Integrated Systems in nanoscale era p.1-6, IEEE Society.

M Taouil, S Hamdioui (2011), Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories, EJ Aas, L. Anghel (Eds.), In 16th IEEE European Test Symposium p.45-50, IEEE Society.

M Taouil, S Hamdioui, E Marinissen (2011), On Modeling and Optimizing Cost in 3D Stacked-ICs, M Sawan, H Harmanani (Eds.), In 6th IEEE International Design and Test Workshop during ICECS 2011 p.24-29, IEEE Society.

M Taouil, S Hamdioui (2011), Stacking Order Impact on Overall 3D Die-to-Wafer Stacked-IC Cost, R Kraemer, A Steininger, A Pawlak, et al. (Eds.), In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems p.335-340, IEEE Society.

M Taouil, S Hamdioui, CIM Beenakker, E Marinissen (2011), Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost, In Journal of Electronic Testing: theory and applications p.1-11.

S Hamdioui, M Taouil (2011), Yield improvement and test cost optimization for 3D stacked ICs, A Chatterjee, A Patra, S Kundu, S Ravi (Eds.), In 20th IEEE Asian Test Symposium 2011 p.480-485, IEEE Society.

L Hasan, Z Al-Ars, M Taouil (2010), High performance and resource efficient biological sequence alignment, s.n. (Eds.), In IEEE EMB p.1767-1770, s.n..

M Taouil, S Hamdioui, E Marinissen (2010), Impact of various test flows on the cost in 3D die-to-wafer stacking, s.n. (Eds.), In Proceedings Intl. test conference 2010 p.1-6, IEEE Society.