AMMO Cortez, G Roelofs, S Hamdioui, G. di Natale (2014), Testing methods for PUF-based secure key storage circuits, In Journal of Electronic Testing: theory and applications Volume 30 p.581-594.

AM Monteiro OliveiraCortez, V van der Leest, R Maes, GJ Schrijen, S Hamdioui (2013), Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs, s.n. (Eds.), In IEEE International symposium on hardware-oriented security and trust p.35-40, IEEE Society.

C Papameletis, B Keller, V Chickermane, EJ Marinissen, S Hamdioui (2013), Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers, s.n. (Eds.), In 18th IEEE European Test Symposium p.1-6, IEEE Society.

MSK Seyab, S Hamdioui, H Kukner, P Raghavan, F Catthoor (2013), Bias temperature instability analysis in SRAM decoder, P Girard, Z Peng (Eds.), In Proceedings 18th IEEE European Test Symposium p.1-1, IEEE Society.

M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik (2013), Impact of mid-bond testing in 3D stacked ICs, s.n. (Eds.), In 16th IEEE Symposium on defect and fault tolerance in VLSI and nanotechnology systems p.1-6, IEEE Society.

M Lefter, GR Voicu, M Taouil, M Enachescu, S Hamdioui, SD Cotofana (2013), Is TSV-based 3D integration suitable for inter-die memory repair?, s.n. (Eds.), In Design, automation & test in Europe conference & exhibition p.1-4, IEEE Society.

S Hamdioui, D Gizopoulos, G Guido, M Nicolaidis (2013), Reliability challenges of real-time systems in forthcoming technology nodes, s.n. (Eds.), In Design, automation & test in Europe conference & exhibition p.1-6, IEEE Society.

M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik (2013), Using 3D-COSTAR for 2.5D test cost optimization, s.n. (Eds.), In IEEE International 3D Systems Integration Conference p.1-8, IEEE Society.

MSK Seyab, S Hamdioui (2013), Variability and reliability analyses in SRAM decoder, s.n. (Eds.), In 4th Workshop on design for reliability p.1-8, s.n..

M Taouil, S Hamdioui, EJ Marinissen, S Bhawmik (2012), 3D-COSTAR: a cost model for 3D stacked ICs, Y Zorian, E Marijnissen, S Hamdioui (Eds.), In Proceedings Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits p.1-6, IEEE.